`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/12/24 11:28:01
// Design Name: 
// Module Name: RRArb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module RRArb_tb();

parameter width = 4;

reg  clk, rst_n;
reg  [width - 1:0] i_g_reg;
wire [width - 1:0] o_p_wire;


RoundRobinArbitor #(
    .N('d4)
) UUT (
    .clk(clk),
    .rst_n(rst_n),
    .i_req(i_g_reg), 
    .o_grant(o_p_wire)
);

initial begin            
    $dumpfile("wave.vcd");
    $dumpvars(0, RRArb_tb);
end

initial begin
    clk = 0; rst_n = 1;
    i_g_reg = 0;
    rst_n = 0; #20 rst_n = 1;
    @(posedge clk) #0 i_g_reg = 4'b0100; #20
    @(posedge clk) #0 i_g_reg = 4'b0000; #20
    @(posedge clk) #0 i_g_reg = 4'b1010; #40
    @(posedge clk) #0 i_g_reg = 4'b1001; #40
    @(posedge clk) #0 i_g_reg = 4'b0000; #100
    @(posedge clk) #0 i_g_reg = 4'b1111; #100
    @(posedge clk) #0 i_g_reg = 4'b0000; #100
    $finish(0);
end

always #10 clk = ~clk;
 
endmodule
